Please use this identifier to cite or link to this item: https://hdl.handle.net/10923/23392
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dc.contributor.authorYan Ghidini de Souza-
dc.contributor.authorThais Christina Webber Dos Santos-
dc.contributor.authorEdson I. Moreno-
dc.contributor.authorIvan Quadros-
dc.contributor.authorRubem Dutra R. Fagundes-
dc.contributor.authorCésar Augusto Missio Marcon-
dc.date.accessioned2022-11-11T20:24:49Z-
dc.date.available2022-11-11T20:24:49Z-
dc.date.issued2012-
dc.identifier.urihttps://hdl.handle.net/10923/23392-
dc.language.isopt_BR-
dc.relation.ispartofProceedings of the 25th Symposium on Integrated Circuits and Systems Design (SBCCI 2012), 2012, Brasil.-
dc.rightsopenAccess-
dc.titleTopological Impact on Latency and Throughput: 2D versus 3D NoC Comparison-
dc.typeconferenceObject-
dc.date.updated2022-11-11T20:24:48Z-
dc.identifier.doiDOI:10.1109/SBCCI.2012.6344439-
Appears in Collections:Apresentação em Evento

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