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Please use this identifier to cite or link to this item: https://hdl.handle.net/10923/13962
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dc.contributor.authorMatheus Trevisan Moreira-
dc.contributor.authorMichel Evandro Arendt-
dc.contributor.authorRicardo Aquino Guazzelli-
dc.contributor.authorNey Laert Vilar Calazans-
dc.date.accessioned2019-02-12T12:04:25Z-
dc.date.available2019-02-12T12:04:25Z-
dc.date.issued2014-
dc.identifier.urihttp://hdl.handle.net/10923/13962-
dc.language.isoen-
dc.relation.ispartofProceedings of the 20th ASYNC 2014, 2014, Alemanha.-
dc.rightsopenAccess-
dc.subjectLow Power-
dc.subjectNull Convention Logic-
dc.subjectStatic Topology-
dc.titleA New CMOS Topology for Low-Voltage Null Convention Logic Gates Design-
dc.typeconferenceObject-
dc.date.updated2019-02-12T12:04:24Z-
Appears in Collections:Apresentação em Evento

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