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Please use this identifier to cite or link to this item: https://hdl.handle.net/10923/13955
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dc.contributor.authorRamy Nagy Tadros-
dc.contributor.authorWeizhe Hua-
dc.contributor.authorMatheus Gibiluka-
dc.contributor.authorMatheus Trevisan Moreira-
dc.contributor.authorNey Laert Vilar Calazans-
dc.contributor.authorPeter Anthony Beerel-
dc.date.accessioned2019-02-11T13:45:40Z-
dc.date.available2019-02-11T13:45:40Z-
dc.date.issued2016-
dc.identifier.urihttp://hdl.handle.net/10923/13955-
dc.language.isoN/A-
dc.relation.ispartofProceedings of the 22nd ASYNC 2016, 2016, Brasil.-
dc.rightsopenAccess-
dc.subjectDelay Lines-
dc.subjectDynamic Voltage Scaling-
dc.titleAnalysis and Design of Delay Lines for Dynamic Voltage Scaling Applications-
dc.typeconferenceObject-
dc.date.updated2019-02-11T13:45:39Z-
Appears in Collections:Apresentação em Evento

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