Campo DC | Valor | Idioma |
dc.contributor.author | Ramy Nagy Tadros | - |
dc.contributor.author | Weizhe Hua | - |
dc.contributor.author | Matheus Gibiluka | - |
dc.contributor.author | Matheus Trevisan Moreira | - |
dc.contributor.author | Ney Laert Vilar Calazans | - |
dc.contributor.author | Peter Anthony Beerel | - |
dc.date.accessioned | 2019-02-11T13:45:40Z | - |
dc.date.available | 2019-02-11T13:45:40Z | - |
dc.date.issued | 2016 | - |
dc.identifier.uri | http://hdl.handle.net/10923/13955 | - |
dc.language.iso | N/A | - |
dc.relation.ispartof | Proceedings of the 22nd ASYNC 2016, 2016, Brasil. | - |
dc.rights | openAccess | - |
dc.subject | Delay Lines | - |
dc.subject | Dynamic Voltage Scaling | - |
dc.title | Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications | - |
dc.type | conferenceObject | - |
dc.date.updated | 2019-02-11T13:45:39Z | - |
Aparece nas Coleções: | Apresentação em Evento
|