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Resultados em Itens:

Data de publicação	Título	Autor(es)
2012	Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects	PONTES, JULIAN; Ney Laert Vilar Calazans; VIVET, PASCAL
2013	H2A: A Hardened Asynchronous Network on Chip	Julian José Hilgemberg Pontes; Ney Laert Vilar Calazans; Pascal Vivet
2014	Schmitt Trigger on Output Inverters of NCL Gates for Soft Error Hardening: is it Enough?	Ricardo Aquino Guazzelli; Guilherme Heck; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2012	An accurate Single Event Effect digital design flow for reliable system level design	PONTES, J.; Ney Laert Vilar Calazans; Pascal Vivet
2013	NCL+: Return-to-One Null Convention Logic	Matheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto; Ney Laert Vilar Calazans
2013	Design of Standard-Cell Libraries for Asynchronous Circuits with the ASCEnD Flow	Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2013	Voltage Scaling on C-Elements: A Speed, Power and Energy Efficiency Analysis	Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2017	Portuguese Personal Story Analysis and Detection in Blogs	Henrique Dias; Vinicius Woloszyn; Renata Vieira
2017	Collective elaboration of a coreference annotated corpus for portuguese texts	Evandro Brasil Fonseca; Sandra Collovini de Abreu; Vinicius Sesti; Ana Luisa Leal; Paulo Quaresma; Renata Vieira
2012	Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes	MOREIRA, MATHEUS T.; GUAZZELLI, RICARDO A.; Ney Laert Vilar Calazans