Repositório PUCRS: Busca

Busca

Resultados 1-9 de 9 (Tempo de busca: 0.001 Segundos).

anterior
1
próximo

Resultados em Itens:

Data de publicação	Título	Autor(es)
2015	A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA Framework	Matheus Gibiluka; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2015	Blade - A Timing Violation Resilient Asynchronous Template	Dylan Hand; Matheus Trevisan Moreira; Hsin-Ho Huang; Danlei Chen; Frederico Butzke; Zhichao Li; Matheus Gibiluka; Melvin Breuer; Ney Laert Vilar Calazans; Peter Anthony Beerel
2015	A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies	Ajay Singhvi; Matheus Trevisan Moreira; Ramy Nagy Tadros; Ney Laert Vilar Calazans; Peter Anthony Beerel
2015	Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits	Guilherme Heck; Leandro Sehnem Heck; Ajay Singhvi; Matheus Trevisan Moreira; Ney Laert Vilar Calazans; Peter Anthony Beerel
2015	A Path Towards Average-Case Silicon via Asynchronous Resilient Bundled-data Design	Peter Anthony Beerel; Ney Laert Vilar Calazans
2015	Performance Optimization and Analysis of Blade Designs Under Delay Variability	Dylan Hand; Hsin-Ho Huang; Benmao Cheng; Yang Zhang; Matheus Trevisan Moreira; Melvin Breuer; Ney Laert Vilar Calazans; Peter Anthony Beerel
2015	Tradeoffs Between RTO and RTZ in WCHB QDI Asynchronous Design	Matheus Trevisan Moreira; Julian José Hilgemberg Pontes; Ney Laert Vilar Calazans
2015	SDDS-NCL Design: Analysis of Supply Voltage Scaling	Ricardo Aquino Guazzelli; Fernando Gehm Moraes; Ney Laert Vilar Calazans; Matheus Trevisan Moreira
2015	TDTB Error Detecting Latches: Timing Violation Sensitivity Analysis and Optimization	Matheus Trevisan Moreira; Dylan Hand; Peter Anthony Beerel; Ney Laert Vilar Calazans