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Results 1-9 of 9 (Search time: 0.001 seconds).
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Issue Date
Title
Author(s)
2014
A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design
Matheus Trevisan Moreira
;
Michel Evandro Arendt
;
Ricardo Aquino Guazzelli
;
Ney Laert Vilar Calazans
2014
Quasi-Delay-Insensitive Return-to-One Design
Matheus Trevisan Moreira
;
Ney Laert Vilar Calazans
2014
Automated Synthesis of Cell Libraries for Asynchronous Circuits
Matheus Trevisan Moreira
;
Michel Evandro Arendt
;
Adriel Ziesemer Jr.
;
Ricardo Augusto da Luz Reis
;
Ney Laert Vilar Calazans
2014
Hardening QDI Circuits Against Transient Faults Using Delay-Insensitive Maxterm Synthesis
Matheus Trevisan Moreira
;
Ricardo Aquino Guazzelli
;
Guilherme Heck
;
Ney Laert Vilar Calazans
2014
Automatic Layout Synthesis with ASTRAN Applied to Asynchronous Cells
Adriel Ziesemer Jr.
;
Ricardo Augusto da Luz Reis
;
Matheus Trevisan Moreira
;
Michel Evandro Arendt
;
Ney Laert Vilar Calazans
2014
A Design Flow for Physical Synthesis of Digital Cells with ASTRAN
Adriel Ziesemer Jr.
;
Ricardo Augusto da Luz Reis
;
Matheus Trevisan Moreira
;
Michel Evandro Arendt
;
Ney Laert Vilar Calazans
2014
Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?
Matheus Trevisan Moreira
;
Augusto Neutzling Silva
;
Mayler Gama Alvarenga Martins
;
André Inácio Reis
;
Renato Perez Ribas
;
Ney Laert Vilar Calazans
2014
Schmitt Trigger on Output Inverters of NCL Gates for Soft Error Hardening: is it Enough?
Ricardo Aquino Guazzelli
;
Guilherme Heck
;
Matheus Trevisan Moreira
;
Ney Laert Vilar Calazans
2014
A monitored NoC with runtime path adaptation
Edson I. Moreno
;
Thais Christina Webber Dos Santos
;
César Augusto Missio Marcon
;
Fernando Gehm Moraes
;
Ney Laert Vilar Calazans
Explore
Author
8
Matheus Trevisan Moreira
4
Michel Evandro Arendt
3
Adriel Ziesemer Jr.
3
Ricardo Aquino Guazzelli
3
Ricardo Augusto da Luz Reis
2
Guilherme Heck
1
André Inácio Reis
1
Augusto Neutzling Silva
1
César Augusto Missio Marcon
1
Edson I. Moreno
.
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Subject
4
Asynchronous Circuits
3
Null Convention Logic
2
Return-to-one
1
Asynchronous Cells
1
asynchronous design
1
Automated Synthesis
1
CAD
1
Cell Synthesis
1
Delay Insensitive Maxterm Synthesis
1
EDA
.
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