1. Repositório PUCRS

Busca


Filtros atuais:

Iniciar uma nova busca
Adicionar filtros:

Use filtros para refinar os resultados da pesquisa.

 | 
Resultados 31-40 de 53 (Tempo de busca: 0.004 Segundos).
Resultados em Itens:
Data de publicaçãoTítuloAutor(es)
2014A Design Flow for Physical Synthesis of Digital Cells with ASTRANAdriel Ziesemer Jr.; Ricardo Augusto da Luz Reis; Matheus Trevisan Moreira; Michel Evandro Arendt; Ney Laert Vilar Calazans
2013Parity Check for m-of-n Delay Insensitive CodesJulian José Hilgemberg Pontes; Ney Laert Vilar Calazans; Pascal Vivet
2014Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?Matheus Trevisan Moreira; Augusto Neutzling Silva; Mayler Gama Alvarenga Martins; André Inácio Reis; Renato Perez Ribas; Ney Laert Vilar Calazans
2013LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell LibrariesMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans; Luciano Copello Ost
2012Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event EffectsPONTES, JULIAN; Ney Laert Vilar Calazans; VIVET, PASCAL
2013H2A: A Hardened Asynchronous Network on ChipJulian José Hilgemberg Pontes; Ney Laert Vilar Calazans; Pascal Vivet
2014Schmitt Trigger on Output Inverters of NCL Gates for Soft Error Hardening: is it Enough?Ricardo Aquino Guazzelli; Guilherme Heck; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2012An accurate Single Event Effect digital design flow for reliable system level designPONTES, J.; Ney Laert Vilar Calazans; Pascal Vivet
2013NCL+: Return-to-One Null Convention LogicMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto; Ney Laert Vilar Calazans
2013Design of Standard-Cell Libraries for Asynchronous Circuits with the ASCEnD FlowMatheus Trevisan Moreira; Ney Laert Vilar Calazans

Descoberta