1. Repositório PUCRS

Browsing by Author Ney Laert Vilar Calazans

Skip to: 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
or enter first few letters:  
Showing rec. 41 to 60 of 78   ◄ previous       next ►  
Issue DateTitleAuthor(s)
2017Go Functional Model for a RISC-V Asynchronous Organization - ARVMarcos Luiggi Lemos Sartori; Ney Laert Vilar Calazans
2013H2A: A Hardened Asynchronous Network on ChipJulian José Hilgemberg Pontes; Ney Laert Vilar Calazans; Pascal Vivet
2017Hardening C-elements Against MetastabilityLeandro Sehnem Heck; Matheus Trevisan Moreira; Ney Laert Vilar Calazans
2014Hardening QDI Circuits Against Transient Faults Using Delay-Insensitive Maxterm SynthesisMatheus Trevisan Moreira; Ricardo Aquino Guazzelli; Guilherme Heck, et al
2012HardNoC: A Platform to Validate Networks on Chip through FPGA PrototypingGuilherme Heck; Ricardo Guazzelli; Fernando Gehm Moraes, et al
2012Impact of C-Elements in Asynchronous CircuitsMatheus Moreira; Bruno Oliveira; Fernando Gehm Moraes, et al
2013Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancyYan Ghidini de Souza; Matheus Moreira; Lucas Brahm, et al
2020Leveraging QDI Robustness to Simplify the Design of IoT CircuitsSARTORI, MARCOS L. L.; WUERDIG, RODRIGO N.; MOREIRA, MATHEUS T., et al
2013LiChEn: Automated Electrical Characterization of Asynchronous Standard Cell LibrariesMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ney Laert Vilar Calazans, et al
2005Mapping Embedded Systems onto NoCs - The Traffic Effect on Dynamic Energy EstimationPALMA, JOSE CARLOS S.; César Augusto Missio Marcon; Fernando Gehm Moraes, et al
2002Modelagem e Descrição de Sistemas Computacionais - Um Estudo de Caso de Comparação das Linguagens VHDL e SDLCésar Augusto Missio Marcon; Ney Laert Vilar Calazans; Fernando Gehm Moraes, et al
2002Modeling of Embedded Digital Systems from SDL Language: a Case StudyCésar Augusto Missio Marcon; Fabiano Passuelo Hessel; Alexandre Amory, et al
2005Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCsCésar Augusto Missio Marcon; José Santanna Palma; Ney Laert Vilar Calazans, et al
2005Models for Embedded Application Mapping onto NoCs: Timing AnalysisCésar Augusto Missio Marcon; KREUTZ, M.; Altamiro Amadeu Susin, et al
2014MoNoC: A monitored network on chip with path adaptation mechanismMORENO, EDSON; Thais Christina Webber Dos Santos; César Augusto Missio Marcon, et al
2013NCL+: Return-to-One Null Convention LogicMatheus Trevisan Moreira; Carlos Henrique Menezes Oliveira; Ricardo Cademartori Porto, et al
2013Parity Check for m-of-n Delay Insensitive CodesJulian José Hilgemberg Pontes; Ney Laert Vilar Calazans; Pascal Vivet
2015Performance Optimization and Analysis of Blade Designs Under Delay VariabilityDylan Hand; Hsin-Ho Huang; Benmao Cheng, et al
2012Power Consumption Reduction in MPSoCs through DFSThiago Raupp da Rosa; Vivian Larréa; Ney Laert Vilar Calazans, et al
2002Prototyping of embedded digital systems from SDL language: a case studyCésar Augusto Missio Marcon; Fabiano Passuelo Hessel; Alexandre Amory, et al
Showing rec. 41 to 60 of 78   ◄ previous       next ►